Static time series analysis includes register to register analysis, I/o analysis and asynchronous reset analysis. To check circuit performance and detect time series disturbances, the time series analyzer USES the time required to obtain the data, the time of arrival of the data and the time of arrival of the hours. To check circuit performance and detect possible time series disturbances, the time series analyzer USES data arrival time, data time, and clock arrival time. For the design to work correctly, the time analyzer shall determine the time ratio and compare the arrival time with the required time.


Check clock Settings
To determine the ratio of path Settings from each registry to the registry, the time series analyzer analyzes each loading and locking edge. The time analyzer shall use the initial edge of the target registry nearest to the lock edge for each lock edge. Figure 1 shows the two configuration relationships, namely setting a and setting b. for the 10ns lock edge, the closest clocks acting as the 10ns lock edge are 3ns and marked as setting a. for the 20ns lock edge, the most recent setting, acting as the 20ns lock edge, is called setting b.


To determine the ratio of path Settings from each registry to the registry, the time series analyzer analyzes each loading and locking edge.

The time analyzer shall set the relaxation of the verification report to hours. Slack meets or does not meet the requirements of the time. A positive value for relaxation indicates that the requirement is met and a negative value indicates that the requirement is not met. The time analyzer calculates the delay in setting the hours between the internal registry and the registry in formula 1.



Check the clock.
The timer analyzer detects every possible configuration of all source pairs and target registers to determine that the clock is in relationship. The time analyzer defines the relationship by comparing all adjacent edges of the clock. The time analyzer checks each setting twice. During the first save check, make sure that the previous lock edge does not capture data running from the current boot edge. It determines that the data initiated by the next boot edge has not been captured by the current lock edge by a second retention check.


The time analyzer shall check all adjacent edges of the clock that establish the relationship to ensure that the relationship is maintained. The time analyzer shall perform two analyses of each setting. During the first save check, make sure that the previous lock edge does not capture data running from the current boot edge. It determines that the data initiated by the next boot edge has not been captured by the current lock edge by a second retention check.

The time analyzer selects the most limited possession ratio possible. Select the ratio between the minimum difference between the lock and the startup edge (i.e., lock - start, not lock - emission absolute), as it determines the minimum delay allowed for communication between registrations.

When using an external discharge device, the logical level pin (dis) is connected to an external resistor (rdis) that can be used to control the discharge of the capacitor, e.g. atavrts2080b.

The formula 4
Data arrival time - time required for data = ageing time

The time required to obtain the data is equal to the time of arrival times multiplied by the uncertainty of time and th.

Network delay at lock edge + to target registry = time of arrival

Delay from startup edge to source registry + delay in network hours + delay in tco + = data arrival time

Using equation 5, the time analyzer calculates the relaxation time of the data path from the input port to the internal registry.


The formula 5

Required data transfer time = closing edge + network hour delay to target registry + MTC

The minimum input delay multiplied by the delay between the input output and the registry is the data arrival time plus the delay at the start edge and the clock network.

The time of arrival of the data is calculated by adding to the source register the delay at the start edge, the delay in the network hours, the minimum delay in input and the delay in output.

Minimum input output delay + input output delay in register = data arrival time + end of start + network clock delay in source register.

Required data transfer time = edge lock + network delay to target registry + th

If the data path is an internal register, the time analyzer stores free time based on equation calculations in equation 6.

The formula 6
Data arrival time - data request time = delay time


The time of arrival of the data is calculated by adding the start edge plus network delay to the source registry and tco plus registry